1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a P channel field effect transistor.
2. Description of the Prior Art
The present invention is applicable to a MOS type semiconductor memory comprising a MOS transistor, and particularly to a MOS dynamic RAM (Random Access Memory).
A description is made hereinafter as to the MOS dynamic RAM which is the background of the present invention.
FIG. 1A is a block diagram showing an example of a simplified circuit of a conventional 1M bit dynamic RAM (Random Access Memory) having 1048576 memory cells. Referring to FIG. 1A, an outline of the basic operation of the dynamic RAM will be hereinafter described.
A clock generator 10 receives an RAS (Row Address Strobe) signal, CAS (Column Address Strobe) signal from a CPU (Central Processing Unit) and generates clock signals .phi..sub.1 and .phi..sub.2. In the normal read/write operation of the dynamic RAM, an address buffer 21 receives external address inputs A.sub.0 to A.sub.9 on a time sharing basis and applies internal address signals A.sub.0 to A.sub.9 on a time share basis to a row decoder 22 and a column decoder 23. The row decoder 22 and the column decoder 23 decode the internal address signals A.sub.0 to A.sub.9 and apply the decoded signals to a memory cell array 25 and an I/O control 24. The writing operation of the input data and the reading operation of the output data are carried out for a memory cell having the address designated as described above. The data in buffer 26 receives the input data and transfers the input data to the memory cell array 25 via the I/O control 24 and the sense amplifiers in response to a clock signal. On the other hand, the data out buffer 27 receives the data from the memory cell array 25 via the sense amplifiers and the I/O control 24 and outputs the output data in response to the clock signal.
FIG. 1B is a block diagram showing a major portion of a conventional dynamic RAM.
Referring to FIG. 1B, the major portion of dynamic RAM comprises an array comprising a plurality of memory cells serving as memory portions, row decoder and a column decoder for selecting an address of each memory cell, and a peripheral circuit portion comprising a sense amplifier connected to data in/out buffers. The plurality of memory cells serving as memory portions are each connected to intersection points of word lines connected to the row decoder and bit lines connected to the column decoder, these word and bit lines constituting a matrix. The above-mentioned array is thus implemented.
Next, an operation of the dynamic RAM is described. When a word line and a bit line are selected by the row decoder and the column decoder in response to a row address signal and a column address signal externally provided, a memory cell at the intersection point of the word line and the bit line is selected, and information is read from or written in the memory cell through the sense amplifier. As to the detail explanation of dynamic RAM, U.S. Pat. No. 3,940,747, entitled "High Density, High Speed Random Access Read-Write Memory" can be referred to.
In this invention, other portion than memory cell 25 in FIG. 1A is to be defined as a peripheral circuit hereinafter.
FIG. 2 is a view showing a cross section of a memory cell in the memory cell portion 25 and an equivalent circuit thereof.
The memory cell portion of the dynamic RAM comprises a transistor and a capacitance. As shown in FIG. 2, the transistor comprises a MOS transistor 31 of an N channel type and the capacitance comprises a cell plate 32 and an N.sup.+ layer 33.
FIG. 3 is a view showing a cross section of a peripheral circuit such as row and column address buffer 21, clock generator circuit 10 and so on, and an equivalent circuit thereof. The peripheral circuit portion generally comprises a CMOS inverter.
The CMOS inverter comprises an N channel transistor TN formed in a p substrate 21 and a P channel transistor TP formed in an n well 1.
FIGS. 4 and 5 are sectional views of a conventional PMOSFET used for a peripheral circuit portion of a dynamic type semiconductor memory device. A gate electrode 3 is formed on a main surface of an N type semiconductor device or an N type well 1 through an insulating film 5 and P.sup.+ diffusion layer 4 serving as a source and a drain is formed beneath both end portions of the gate electrode 3 and on the main surface of the substrate 1. The P.sup.+ diffusion layer is formed by ion implantation of B or BF.sub.2. A wiring layer 6 is connected to the source and the drain. Ion implantation is made of B or BF.sub.2 in an connection portion 7 to lower a contact resistance.
The formed elements are isolated by an element isolating layer 2.
Next, a description is made of operation. A predetermined voltage is applied to the gate electrode 3. As a result, a P type channel is formed beneath the gate electrode 3, which connects the source 4 to the drain 4. Then, selection is made of a desired memory cell to and from which data is written and read.
Conventionally, the source and drain of the PMOSFET have been formed by ion implantation of B and BF.sub.2. A light ion such as B or BF.sub.2 causes a channeling phenomenon on the occasion of ion implantation. The term of "channeling" means that a tunnel is formed in a constant direction of a crystalline axis of a substrate. The channeling causes a problem in which a projection distance of the implanted ion cannot be constant. As a result, a shallow P.sup.+ layer is not formed. In order to form a shallow P.sup.+ layer, silicon must be implanted in advance on the substrate to prevent the channeling. On the other hand, B.sup.+ has a large diffusion coefficient as compared with As.sup.+. Therefore, it is necessary that annealing is performed at a lower temperature. However, in case where silicon has been implanted on the substrate, annealing needs to be preformed at a higher temperature, because damage due to the silicon implantation was caused on the substrate.
Consequently, the P.sup.+ layer forms only a deep layer as compared with N.sup.+ layer. Therefore, it is difficult to form the PMOSFET having a small channel dimension.
On the other hand, when a contact portion connecting the source and drain portion to the wiring is formed, B and BF.sub.2 are implanted after a contact hole is formed in order to lower a contact resistance. FIG. 5 shows the contact portion of the source and drain of the conventional PMOSFET.
As described above, B and BF.sub.2 generate the channeling on the occasion of implantation and also have a long diffusion length. When B and BF.sub.2 are implanted to the contact portion, the P.sup.+ layer is diffused beneath the gate electrode which is adjacent to the contact portion. As a result, the channel length of the PMOSFET becomes short, so that it is difficult to make the PMOSFET small.